第2篇 ic设计验证工程师岗位职责

ic设计验证工程师 西安紫光国芯半导体有限公司 西安紫光国芯半导体有限公司,华芯半导体,西安紫光国芯,西安紫光国芯半导体有限公司,紫光国芯 以下招聘职位均为公司设计服务部门的工程师职位,为上海大型国际ic公司以及国内顶端ic公司提供on-site设计服务。

西安紫光国芯的设计服务部门能够提供高端设计服务,具备从设计规格到芯片流片完整流程的设计经验,包括:设计实现、功能验证、综合和dft、物理实现、时序和物理检查、流片。公司在过去几年中成功为客户完成了十几款soc在65nm/40nm/28nm/14nm工艺上的soc芯片设计和流片,帮助客户低成本的、高效的实现产品化,是目前国内最大的设计服务外包服务商,所服务的客户均为国际知名大型芯片设计公司以及国内顶端芯片设计公司,具备一流的技术及设计环境以及良好的文化氛围,我们的员工在客户端承担核心技术板块,使其可以快速稳定成长。

我们各个业务板块均提供先进的设计开发环境,良好的企业文化以及人文关怀,优厚的薪酬待遇,完善的休假体系,全面的社会及商业保险。诚邀有志ic事业的人才加盟共同发展!

responsibilities:

1. according to the design specification, be responsible for the verification plan and verification objective definition.

2. test-bench development (modeling, assertions, checkers, monitors, score-board, regressions, coverage), test-case development (sequence, vrad) and integration.

3. work with random verification methodology(vmm, ovm, uvm, erm)

4. work as an independent verification engineers to check the design functionality at soc module level and chip level.

5. work as interface with front-end and back-end engineer to optimize or review the design architecture and implementation.

6. verilog or vhdl coding according to design specification or external/internal ip integration.

7. support the post simulation with gate-level verilog or vhdl net list.

requirements:

1. either bachelor, master or phd in microelectronics, electronic engineering, or related field, 2+ years of verification working experience.

2. experience with verification language (specman/e-language, system-verilog, vera)

3. experience with rtl coding and simulators (modelsim, nc-sim).

4. basic knowledge of script language (perl, tcl, c-language and so on)

5. knowledge about 2g/3g/lte handset baseband architecture, arm, ahb architecture is a plus.

6. knowledge about baseband chip peripheral (usb2.0/usb3.0, ssic, mipi) is a plus.

7. team oriented, love to work in young, international and highly motivated teams.

8. good command of english