第5篇 高级ic设计工程师岗位职责

1.​participate in riscv or deep learning accelerator or other soc ip design for all frontend phase

2.​specification define

3.​rtl implementation

4.​analysis and optimization for performance

5.​analysis and optimization for power

6.​analysis and optimization for timing

7.​design flow: lint/synthesis/sta/formal check

8.​silicon debugging

任职条件

1.​ms with 5+ or 3+ years of experience in asic design

2.​experience with risc cpu (riscv/mips/arm) related ips design are highly desirable

3.​experience with usb/mipi_csi/mipi_dsi or other high speed interface ips design are highly desirable

4.​experience with deep learning accelerator related ips design are highly desirable

5.​experience with all phases of frontend architecture, design and validation

6.​rtl coding, design reviews, syn, cdc, fev

7.​demonstrated work experience with timing analysis, area and power optimizations, performance analysis, debug ability, ecos, and post-silicon debug

8.​excellent knowledge of verilog and popular eda simulation & implementation tools

9.​good experience in scripting languages like perl, unix shell or similar languages