第4篇 半导体集成电路工程师岗位职责

ic layout design engineer 半导体集成电路版图设计工程师 description as an ic layout design engineer at micron's shanghai design center, you will work in a highly innovative and motivated design team using state of the art memory technologies to advance dram memory design. as part of a multi-disciplinary team, you will contribute to physical layout floor plan of various memory chip circuit blocks, and perform block level layout, lvs/drc verification and using other cad tools to check layout. of course you will also work closely with micron's various design teams in us and other countries and leverage vast resources available throughout micron’s global sites. additionally, you will perform verification (lvs/drc etc) of layout to the full-chip level, and assist in project tape out. requirement -college degree (or above) in electrical engineering or other related engineering field. -3 to 5 years of ic custom layout working experience (more experienced engineers highly welcome). -proficiency with cadence oa and calibre verification tools desirable. -understanding of basic cmos circuits is a plus. -understanding of dram/flash architecture or previous memory layout experience is a plus. -english language skill in writing and speaking is a plus. -no fresh graduates will be considered. education college degree (or above) in electrical engineering or other related engineering field.